1. Technology Field
The present invention relates to a data writing method for a rewritable non-volatile memory module, a memory controller and a memory storage apparatus using the method.
2. Description of Related Art
Along with the widespread of digital cameras, cell phones, and MP3 in recently years, the consumers' demand for storage media has increased drastically. Since a rewritable non-volatile memory is characterized by non-volatility of data, low power consumption, small volume, non-mechanical structure, and fast reading and writing speed, the rewritable non-volatile memory is the most adaptable memory to be applied in a portable electronic product, e.g., a notebook computer. A solid state drive is a storage apparatus adopting flash memory as storage medium. Therefore, the flash memory industry has become a very popular part of the electronic industry in recent years.
A flash memory module has a plurality of physical erasing units, and each of the physical erasing units has a plurality of physical programming units, wherein data must be written into physical programming units according to the sequence of the physical programming units in the physical erasing unit. In addition, a physical programming unit containing data has to be erased before it is used for writing new data. Particularly, each physical erasing unit is the smallest erasing unit, and each physical programming unit is the smallest programming (i.e., writing) unit. Therefore, in the management of the flash memory module, the physical erasing units are grouped into a data area and a spare area.
The physical erasing units of the data area are used for storing data written by the host system 1000. To be more specific, a memory management circuit in a memory storage apparatus converts a logical access address accessed by the host system into a logical page of a logical block and maps the logical page of the logical block to a physical programming unit of a physical erasing unit in the data area. Namely, in the management of a flash memory module, the physical erasing units in the data area are deemed used physical erasing units (e.g., the physical erasing units already contain data written by the host system). For example, the memory management circuit records the mapping relationship between the logical blocks and the physical erasing units in the data area in a logical-to-physical address mapping table, wherein the logical pages of each logical block are sequentially mapped to the physical programming units of the corresponding physical erasing unit.
And, the physical erasing units of the spare area are used for substituting the physical erasing units of the data area. In particular, a physical erasing unit already containing data has to be erased before it is used for writing new data, while a physical erasing unit in the spare area is used for writing updated data in replacement of the physical erasing unit originally mapped to a logical block. Hence, the physical erasing units in the spare area are either blank or usable physical erasing units (i.e., these physical erasing units do not contain data, or these physical erasing units contain data marked as invalid data).
Namely, the physical programming units of the physical erasing units in the data area and the spare area alternately map the logical pages of the logical blocks for containing data written by the host system. For example, the memory management circuit of the memory storage apparatus takes at least a physical erasing unit from the spare area as a global random physical erasing unit, and when the logical access address storing the updated data desired to be written by the host system corresponds to a logical page of a logical block in the storage apparatus, the memory management circuit in the storage apparatus writes the updated data into the physical programming units of the global random physical erasing unit.
In particular, during the operation of memory storage apparatus, when the global random physical erasing units will be exhausted, the memory management circuit of the memory storage apparatus copies data stored in the global random physical erasing units to the corresponding physical erasing units (referred to as “the valid data merging operation”), thereby releasing the storage space of the global random physical erasing units to execute next write commands. After copying the data stored in the global random physical erasing units to the corresponding physical erasing units, the memory management circuit of the memory storage apparatus may update the logical-to-physical address mapping table such that follow-up access operations can be performed successfully. Because the capacity of a memory storage apparatus is more and more large, a plurality of logical-to-physical address mapping tables are used for recording mappings of all logical blocks and physical erasing units. Accordingly, when the valid data merging operation must be performed first before a write command from a host system is executed, operations of loading and restoring different logical-to-physical address mapping tables to recording mapping information into the logical-to-physical address mapping tables may be performed and therefore a delay for executing write command may be occurs, thereby influencing the performance of the memory storage apparatus.
Nothing herein should be construed as an admission of knowledge in the prior art of any portion of the present invention. Furthermore, citation or identification of any document in this application is not an admission that such document is available as prior art to the present invention, or that any reference forms a part of the common general knowledge in the art.